Polysilicon structure, thin film transistor panel using the same, and manufacturing method of the same

ABSTRACT

A method for forming a polysilicon structure is provided. An amorphous silicon structure with a first amorphous silicon region and a second amorphous silicon region is formed in a first region and a second region of a substrate, respectively. The first amorphous silicon region is thinner than the second amorphous silicon region. The amorphous silicon structure is crystallized to form the polysilicon structure with a first polysilicon region and a second polysilicon region corresponding to the first amorphous silicon region and the second amorphous silicon region.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of pending U.S. patent applicationSer. No. 11/000,837, filed Nov. 30, 2004 and entitled “POLYSILICONSTRUCTURE, THIN FILM TRANSISTOR PANEL USING THE SAME, AND MANUFACTURINGMETHOD OF THE SAME,” the contents of which are incorporated herein byreference.

BACKGROUND

The present invention relates to a low temperature polysilicon film andin particular to a polysilicon structure formed by crystallization of anamorphous silicon structure, methods for forming the same, and devicesutilizing the film.

Typically, thin film transistors (TFTs) are used as the active devicesin active matrix flat panel displays. For example, TFTs are employed todrive the liquid crystal display (LCD) or the organic light emittingdisplay (OLED).

Conventionally, hydrogenated amorphous silicon (α—Si: H) is used as thesemiconductor film (active layer) of a TFT. Polysilicon, however, mayprovide higher electron transmission than amorphous silicon due to moreregular crystal orientation. Thus a development trend is to utilize thepolysilicon instead of amorphous silicon in TFT technology.

Typically, there are three methods for forming the thin polysiliconfilm. In a first method, the polysilicon film is formed by deposition.In this method, the polysilicon film requires a sufficient thickness, soas to grow large grains. Thus, the polysilicon film has a poor surfaceuniformity that adversely affects the formation of the subsequent gateinsulating layer. Moreover, the deposition temperature is high (600°C.), which also adversely affects the fabrication of the device. In asecond method, thermal treatment is performed on an amorphous siliconlayer, so as to transfer to a polysilicon layer. In this method, thepolysilicon layer may be less thick and have a better surfaceuniformity. However, a high deposition temperature (6002C) and longdeposition duration are required and the thermal budget increases. As aresult, throughput and device reliability suffer. In a third method,perform a laser treatment to transfer an amorphous silicon layer into apolysilicon layer. The method is the most commonly used.

The polysilicon TFT display comprises a display region and a drivingcircuit region, wherein the switching devices on the driving circuitregion require higher switching rate and readability. That is, theswitching devices on the driving circuit region preferably have higherelectron transmission and better sub-threshold swing. A polysiliconlayer with large grain size can provide such electronic characteristics.Additionally, current leakage in the display region must be low. If thesurface roughness of the polysilicon layer is too high, poor coverage ofthe gate insulating layer thereon results, thus increasing currentleakage. If the grain size of the polysilicon layer is small, lowsurface roughness results, improving the coverage of the gate insulatinglayer thereon and reducing current leakage. That is, in order to improvethe electronic characteristics of the polysilicon TFT display, thepolysilicon layer on the driving circuit region must have a relativelylarge grain size and that on the display region a relatively small grainsize.

In order to form a polysilicon film with different grain sizes on thedriving circuit region and the display region, respectively, forfabrication of the polysilicon TFT display, the driving circuit regionand the display region must be respectively treated. For example, alaser treatment with a relatively low scanning rate is performed on theamorphous silicon layer on the driving circuit region, to form thepolysilicon layer with a relatively large grain size. The lasertreatment with a relatively high scanning rate is subsequently performedon the amorphous silicon layer on the display region, to form thepolysilicon layer with relatively small grain size. The problemspresented by laser alignment and mask changes may reduce yield andthroughput. Thus, an improved method for forming polysilicon layers withdifferent grain sizes is desirable.

SUMMARY

Embodiments of the invention provide a polysilicon structure on asubstrate. The polysilicon structure comprises a first polysiliconregion and a second polysilicon region. A thickness of the firstpolysilicon region is less than that of the second a thickness and agrain size of the first polysilicon region is larger than that of thesecond polysilicon region.

Embodiments of the invention additionally provide a method for forming apolysilicon structure. A substrate having a first region and a secondregion is provided. An amorphous silicon structure with a firstamorphous silicon region and a second amorphous silicon region is formedin the first region and the second region, respectively. The firstamorphous silicon region is thinner than the second amorphous siliconregion. The amorphous silicon structure is crystallized to form thepolysilicon structure with a first polysilicon region and a secondpolysilicon region corresponding to the first and second amorphoussilicon regions, respectively.

Embodiments of the invention further provide a method for forming apolysilicon structure. A substrate having a first region, a secondregion, and a third region is provided. An amorphous silicon layer witha first amorphous silicon region, a second amorphous silicon region, anda third amorphous silicon region, is formed on the substrate, in whichthe first, second and third amorphous silicon regions, are respectivelyin the first region, the second region and the third region. The firstamorphous silicon region is thinner than the second amorphous siliconregion, which is thinner than the third amorphous silicon region. Theamorphous silicon structure is crystallized to form the polysiliconstructure with a first polysilicon region, a second polysilicon regionand a third polysilicon region corresponding to the first, second andthird amorphous silicon regions, respectively.

Embodiments of the invention still further provide a flat panel display.The display comprises a first transistor and a second transistor. Thefirst transistor is disposed on the substrate and comprises a firstpolysilicon region serving as a first active region. The secondtransistor is disposed on the substrate and comprises a secondpolysilicon region serving as a second active region. Moreover, thefirst polysilicon region is thinner than the second polysilicon regionand a grain size of the first polysilicon region is larger than that ofthe second polysilicon region.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will become more fully understood from thedetailed description given hereinbelow and the accompanying drawings,given by way of illustration only and thus not intended to be limitativeof the invention.

FIGS. 1A to 1C are cross-sections of a method for forming a polysiliconstructure of the first embodiment of the present invention.

FIGS. 2A to 2D are cross-sections of a method for forming a polysiliconstructure of the second embodiment of the present invention.

FIGS. 3A to 3B are cross-sections of a method for forming a polysiliconstructure of the third embodiment of the present invention.

FIGS. 4A to 4C are cross-sections of a method for forming thin filmtransistors for a flat panel display of the fourth embodiment of thepresent invention.

DETAILED DESCRIPTION

In the first embodiment, as shown in FIG. 1A, a substrate 100 comprisinga driving circuit region 1 and a display region 2 is provided. A firstamorphous silicon layer 110 is formed on the substrate 100 correspondingto the display region 2 of the substrate 100 by deposition, lithography,and etching. For example, an amorphous silicon layer (not shown) isformed by chemical vapor deposition (CVD). Thereafter, lithography andetching are performed on the amorphous silicon layer to form the firstamorphous silicon layer 110 in the display region 2 of the substrate100, wherein the etching may comprise wet or dry etching.

A second amorphous silicon layer 120 is subsequently formed on thesubstrate 100 corresponding to the driving circuit region 1 of thesubstrate 100 and covers the first amorphous silicon layer 110 in thedisplay region 2, as shown in FIG. 1B. As a result, an amorphous siliconstructure with a first amorphous silicon region 121 a in the drivingcircuit region 1 and a second amorphous silicon region 121 b in thedisplay region 2 is formed on the substrate 100. The difference inthickness between the first amorphous silicon region 121 a in thedriving circuit region 1 and the second amorphous silicon region 121 bin the display region 2 must be maintained within a specific range. Ifthe difference in thickness of the first amorphous silicon region 121 aand the second amorphous silicon region 121 b is too low, the differencein grain size therebetween is small, thus, the electroniccharacteristics of the polysilicon TFT are reduced. Conversely, if thedifference in thickness of the first amorphous silicon region 121 a andthe second amorphous silicon region 121 b is too high, furtheradjustment of process conditions is required, such as the ion implantingenergy and dosage, complicating the process. Therefore, the differencein thickness must be maintained within a range of about 100 to 1000 Å,and preferably 200 to 400 Å.

The amorphous silicon structure is crystallized. That is,crystallization is simultaneously performed on the first and secondamorphous silicon regions 121 a and 121 b, such that the amorphoussilicon structure is transferred into a polysilicon structure 130 with afirst polysilicon region 130 a and a second polysilicon region 130 bcorresponding to the first amorphous silicon region 121 a and a secondamorphous silicon region 121 b, respectively, as shown in FIG. 1C. Insome embodiments, the crystallization may comprise a laser treatmentthat employs, for example, an excimer laser, continuous wave laser (CWlaser), or laser beam pulse. Moreover, the laser treatment may compriselateral solidification (LS), sequential lateral solidification (SLS),continuous grain silicon (CGS), or metal induced lateral crystallization(MILC).

Since the thickness of the second amorphous silicon layer 120 in thedriving circuit region 1 is less than the total thickness of the firstand second amorphous silicon layers 110 and 120 in the display region 2,the meltability of the second amorphous silicon layer 120 in the drivingcircuit region 1 after the laser treatment, is higher than that of thefirst and second amorphous silicon layers 110 and 120 in the displayregion 2. Accordingly, the first polysilicon region 130 a in the drivingcircuit region 1 can be formed with larger grain size, therebyeffectively improving electron mobility and sub-threshold swing.Conversely, since the total thickness of the first and second amorphoussilicon layers 110 and 120 in the display region 2 is thicker than thatof the second amorphous silicon layer 120 in the driving circuit region1, the meltability of the first and second amorphous silicon layers 110and 120 in the display region 2 after the laser treatment, is lower thanthat of the second amorphous silicon layer 120 in the driving circuitregion 1. Accordingly, the second polysilicon region 130 b in thedisplay region 2 can be formed with smaller grain size, thereby loweringthe surface roughness of the polysilicon layer 130 in the display region2 to reduce current leakage. In the first embodiment, the mentionedpotential advantages can be obtained with one laser treatment procedure,eliminating problems presented by laser alignment and mask changes, thusreducing process time.

In the second embodiment, as shown in FIG. 2A, a substrate 200comprising a driving circuit region 3 and a display region 4 isprovided. A first amorphous silicon layer 210 is formed on the substrate200. For example, the amorphous silicon layer 210 is formed by chemicalvapor deposition (CVD).

Thereafter, the first amorphous silicon layer 210 in the driving circuitregion 3 is partially removed by lithography and etching to form thefirst amorphous silicon layer 210 with differing thicknessesrespectively in the driving circuit region 3 and display region 4, asshown in FIG. 2B. Here, the etching may comprise wet or dry etching.Moreover, the difference in thickness between the first amorphoussilicon layer 210 in the driving circuit region 3 and that in thedisplay region 4 must be maintained within a specific range.

A second amorphous silicon layer 220 is subsequently formed on the firstamorphous silicon layer 210 in the driving circuit region 3 and thedisplay region 4, as shown in FIG. 2C. As a result, an amorphous siliconstructure with a first amorphous silicon region 221 a in the drivingcircuit region 3 and a second amorphous silicon region 221 b in thedisplay region 4 is formed on the substrate 100. Since the difference inthickness between the first amorphous silicon layer 210 in the drivingcircuit region 3 and that in the display region 4 is maintained within aspecific range, the difference in thickness can be maintained within aspecific range after forming the second amorphous silicon layer 220 onthe first amorphous silicon layer 210. As mentioned, if the differencein thickness is too low, the difference in grain size between thesubsequently formed polysilicon silicon layer in the driving circuitregion 3 and that in the display region 4 is small, reducing theelectronic characteristics of the polysilicon TFT. Conversely, if thedifference in thickness is too high, further adjustment of processconditions is required, such as the ion implanting energy and dosage,complicating the process. Thus, the difference in thickness must bemaintained within a range of about 100 to 1000Å, and preferably 200 to400 Å.

The amorphous silicon structure is crystallized. That is,crystallization is simultaneously performed on the first and secondamorphous silicon regions 221 a and 221 b, such that the amorphoussilicon structure is transferred into a polysilicon structure 230 with afirst polysilicon region 230 a and a second polysilicon region 230 bcorresponding to the first amorphous silicon region 221 a and a secondamorphous silicon region 221 b, respectively, as shown in FIG. 2D. Inthe second embodiment, the crystallization may comprise a lasertreatment that employs, for example, an excimer laser, continuous wavelaser (CW laser), or laser beam pulse. Moreover, the laser treatment maycomprise lateral solidification (LS), sequential lateral solidification(SLS), continuous grain silicon (CGS), or metal induced lateralcrystallization (MILC).

Since the thickness of the second amorphous silicon layer 220 in thedriving circuit region 3 is less than the total thickness of the firstand second amorphous silicon layers 210 and 220 in the display region 4,the meltability of the second amorphous silicon layer 220 in the drivingcircuit region 3 after the laser treatment, is higher than that of thefirst and second amorphous silicon layers 210 and 220 in the displayregion 4. Accordingly, the first polysilicon region 230 a in the drivingcircuit region 3 can be formed with larger grain size, therebyeffectively improving electron mobility and sub-threshold swing.Conversely, since the total thickness of the first and second amorphoussilicon layers 210 and 220 in the display region 4 is greater than thatof the second amorphous silicon layer 220 in the driving circuit region3, the meltability of the first and second amorphous silicon layers 210and 220 in the display region 4 after the laser treatment, is lower thanthat of the amorphous silicon layer 220 in the driving circuit region 3.Accordingly, the second polysilicon region 230 b on the display region 4can be formed with smaller grain size, thereby lowering the surfaceroughness of the polysilicon layer 230 in the display region 4 to reducecurrent leakage. In the second embodiment, the mentioned potentialadvantages can be obtained with one laser treatment procedure,eliminating problems presented by laser alignment and mask changes, thusreducing process time.

In the third embodiment, as shown in FIG. 3A, a substrate 300 comprisinga first region 5, a second region 6 and a third region 7 is provided. Anamorphous silicon structure 310 with a first amorphous silicon region310 a in the first region 5, a second amorphous silicon region 310 b inthe second region 6 and a third amorphous silicon region 310 c in thethird region 7 is formed on the substrate 300, wherein the thicknessesof the amorphous silicon structure 310 in the first, second, and thirdregions 5, 6, and 7 are different. For example, the first amorphoussilicon region 310 a in the first region 5 has a thickness less thanthat of the third amorphous silicon region 310 c in the third region 7,and the second amorphous silicon region 310 b in the second region 6 hasa thickness between that of the first and third amorphous siliconregions 310 a and 310 c in the first and third regions 5 and 7.

The difference in thickness between the amorphous silicon structure 310in the first region 5 and the third region 7 must be maintained within aspecific range. If the difference in thickness is too low, thedifference in grain size between the subsequently formed polysiliconsilicon structure in different regions is small, thus the electroniccharacteristics of the polysilicon TFT are reduced. Conversely, if thedifference in thickness is too high, further adjustment of processconditions is required, such as the ion implanting energy and dosage,complicating the process. In the third embodiment, the difference inthickness may be maintained within a range of about 100 to 1000 Å, andpreferably 200 to 400 Å.

The amorphous silicon structure 310 is crystallized. That is,crystallization is simultaneously performed on the first, second, andthird amorphous silicon regions 310 a, 310 b, and 310 c, such that theamorphous silicon structure 310 is transferred into a polysiliconstructure 330 with a first polysilicon region 330 a, a secondpolysilicon region 330 b, and a third polysilicon region 330 ccorresponding to the first, second, and third amorphous silicon regions310 a, 310 b, and 310 c, respectively, as shown in FIG. 3B. In the thirdembodiments, the crystallization may comprise a laser treatment thatemploys, for example, an excimer laser, continuous wave laser (CWlaser), or laser beam pulse. Moreover, the laser treatment may compriselateral solidification (LS), sequential lateral solidification (SLS),continuous grain silicon (CGS), or metal induced lateral crystallization(MILC).

Since the thicknesses (surface levels) of the amorphous siliconstructure 310 in the first, second, and third regions 5, 6, and 7 aresuccessively increased, the meltability of the amorphous siliconstructure 310 in the first, second, and third regions 5, 6, and 7 aresuccessively decreased after the laser treatment. Accordingly, the grainsizes and surface roughness of the subsequently formed polysilicon layer330 in the first, second, and third regions 5, 6, and 7 are successivelydecreased. That is, the polysilicon structure 330 with different grainsizes in different regions 5, 6, and 7 can be accomplished by performingone laser treatment procedure on the amorphous silicon structure 310having different thicknesses in different regions 5, 6, and 7, therebyeliminating problems presented by laser alignment and mask changes, thusreducing process time.

In the fourth embodiment, as FIG. 4C illustrates, thin film transistorsfor a flat panel display are provided. The thin film transistors aredisposed on a substrate 400 comprising a driving circuit region 8 and adisplay region 9. A polysilicon structure 430 with a first polysiliconregion 410 a and a second polysilicon region 410 b is disposed on thesubstrate 400. The first and second polysilicon regions 410 a and 410 bhave different thickness and grain sizes. For example, the firstpolysilicon region 430 a in the driving circuit region 8 is thinner, hasa larger grain size, and a higher surface roughness than that of thesecond polysilicon region 430 b in the display region 9, therebyimproving electron mobility and sub-threshold swing of the thin filmtransistor in the driving circuit region 8 and reducing current leakageof the thin film transistor in the display region 9.

FIGS. 4A to 4C illustrate a method for forming thin film transistors fora flat panel display of the fourth embodiment of the present invention.As shown in FIG. 4A, a substrate 400 comprising a driving circuit region8 and a display region 9 is provided. A buffer layer 405 is subsequentlyformed on the substrate 400. An amorphous silicon structure 410 with afirst amorphous silicon region 410 a and a second amorphous siliconregion 410 b is formed on the buffer layer 405. The first amorphoussilicon layer 410 a in the driving circuit region 8 has a thickness lessthan that of the second amorphous silicon region 410 b in the displayregion 9. The difference in thickness between the amorphous siliconstructure 410 in the driving circuit region 8 and that in the displayregion 9 may be maintained within a specific range. For example, thedifference in thickness may be maintained within a range of about 100 to1000 Å, and preferably 200 to 400 Å.

Thereafter, crystallization is simultaneously performed on the amorphoussilicon structure 410 in the driving circuit region 8 and the displayregion 9, such that the amorphous silicon structure 410 is transferredinto a polysilicon structure 430, as shown in FIG. 4B. In thisembodiment, the crystallization may comprise a laser treatment whichemploys, for example, an excimer laser, continuous wave laser (CWlaser), or laser beam pulse. Moreover, the laser treatment may compriselateral solidification (LS), sequential lateral solidification (SLS),continuous grain silicon (CGS), or metal induced lateral crystallization(MILC).

Gate insulating layer 440 is formed on the polysilicon structure 430.Gates 450 is subsequently formed on the gate insulating layer 440, asshown in FIG. 4B. Thereafter, ion implantation is performed on thepolysilicon layer 430 using the gates 450 as masks to form sources S,drains D, and channels C.

An interlayer dielectric (ILD) layer 460 is formed on the gateinsulating layer 440 and covers the gates 450. Next, interconnects 470are formed in the ILD layer 460, as shown in FIG. 4C. Finally, processesfor fabricating the flat panel display are then successively proceededand the flat panel display (not shown) is complete.

While the invention has been described by way of example and in terms ofpreferred embodiments, it is to be understood that the invention is notlimited thereto. To the contrary, it is intended to cover variousmodifications and similar arrangements (as would be apparent to thoseskilled in the art). Therefore, the scope of the appended claims shouldbe accorded the broadest interpretation to encompass all suchmodifications and similar arrangements.

1. A thin film transistor panel, comprising: a substrate; a firsttransistor disposed on the substrate and comprising a first polysiliconregion serving as a driving circuit region; and a second transistordisposed on the substrate and comprising a second polysilicon regionserving as a display region, wherein the second polysilicon region isformed by a single layer; wherein the entire first polysilicon region isthinner than the entire second polysilicon region and a grain size ofthe entire first polysilicon region is larger than that of the entiresecond polysilicon region.
 2. The panel as claimed in claim 1, whereinthe difference in thickness between the first polysilicon region and thesecond polysilicon region is about 100 to 1000 Å.
 3. The panel asclaimed in claim 1, wherein the difference in thickness between thefirst polysilicon region and the second polysilicon region is about 200to 400 Å.
 4. The panel as claimed in claim 1, wherein the firstpolysilicon region has a surface roughness higher than that of thesecond polysilicon region.